1. Field of the Invention
The present invention relates to an apparatus for dividing a bank in a flash memory and, more particularly, to an apparatus for dividing a bank in a NAND flash.
2. Discussion of Related Art
A conventional NAND flash memory can be implemented with a very small cell area and is thus suitable for high-integrated memory devices. This type of the flash memory, however, requires long time to read a first data and also needs long time for programming. Furthermore, the conventional flash memory has a disadvantage that it could not perform one operation while the other operation is performed.
FIG. 1 is a conceptual view illustrating the structure of a bank in a conventional NAND flash memory.
Referring to FIG. 1, a page buffer 20 and a cache buffer 30 are intervened between a NAND flash memory bank 10 and an input/output line 40. Data inputted via the cache buffer 30 are sent to the page buffer 20. Data for performing a next page program, while a selected page is being programmed, is transferred to the cache buffer 30. It is thus possible to improve the speed of the read operation and the program operation in a conventional single bank structure. By using the cache buffer 30, the data input operation can be simultaneously performed while the program operation is being performed and a next page can be read out to the page buffer 20 while the data is being outputted. In this case, however, there still remains a problem that other operations could not be performed while the read, program or erase operation is performed.